74HC40103 DATASHEET PDF

It has control inputs for enabling or disabling the clock CP , for clearing the counter to its maximum count and for presetting the counter either synchronously or asynchronously. In normal operation, the counter is decremented by one count on each positive-going transition of the clock CP. When the synchronous preset enable input PE is LOW, data at the jam input P0 to P7 is clocked into the counter on the next positive-going clock transition regardless of the state of TE. The jam inputs P0 to P7 represent a single 8-bit binary word.

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It has control inputs for enabling or disabling the clock CP , for clearing the counter to its maximum count and for presetting the counter either synchronously or asynchronously. In normal operation, the counter is decremented by one count on each positive-going transition of the clock CP. When the synchronous preset enable input PE is LOW, data at the jam input P0 to P7 is clocked into the counter on the next positive-going clock transition regardless of the state of TE.

The jam inputs P0 to P7 represent a single 8-bit binary word. When the master reset input MR is LOW, the counter is asynchronously cleared to its maximum count decimal regardless of the state of any other input. If all control inputs except TE are HIGH at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of clock pulses long.

Device may be cascaded using the TE input and the TC output, in either a synchronous or ripple mode. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Features and benefits.

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